Since there was some updates today and it looked like SPI was involved I hoped things magically sped up. So far I don't see any speedups. Looking at the Logic Analyzer timings still showed that the Frequency was about 6.25mhz and still have large gap in between bytes.
So I did some hacking on MRAA to see if I find anything. I tried to see if changing using a write instead of the IOCTL to output the buffers, no change. I thought maybe the fact that MRAA did not set the max speed but instead passed it in each packet, might be something so I tried setting the max as well.
Out of curiosity at device start I did a IOCTL to do a query of the max speed, which I output in a printf. It printed: Max Speed 6250000
Again I tried actually setting this speed, and printed out what the result:
mraa_result_t
mraa_spi_frequency(mraa_spi_context dev, int hz)
{
dev->clock = hz;
#if 1
uint32_t ulMaxSpeed = hz;
ioctl(dev->devfd, SPI_IOC_WR_MAX_SPEED_HZ, &ulMaxSpeed);
ioctl(dev->devfd, SPI_IOC_RD_MAX_SPEED_HZ, &ulMaxSpeed);
printf("Try %u Max Speed %u\n", hz, ulMaxSpeed);
#endif
return MRAA_SUCCESS;
}
What I saw was: Try 8000000 Max Speed 6250000
So so far it looks like I can not update to any faster speed. Is there some other external setting to allow it to go faster? Also wonder if there is a setting for inter byte gap?